In conventional LSIs, elements were configured integrally in a two-dimensional plane on a silicon substrate. Therefore, there is no way other than reducing (miniaturizing) a size of an element to increase a storage capacity of a memory. However, recently, the miniaturization becomes difficult in cost as well as technically.
To solve the problem, there is proposed an idea of manufacturing a three-dimensionally laminated memory by laminating memory layers three-dimensionally and collectively processing the memory layers. Further, there is proposed a pipe-shaped NAND type flash memory in which a U-shaped NAND string is formed in a laminate direction as the collectively-processed-type three-dimensionally laminated memory (pipe-shaped bit cost scalable (p-BiCS)). In the pipe-shaped NAND type flash memory, a NAND string is configured of a pair of silicon pillars and a pipe for coupling the silicon pillars in lower ends. More specifically, a memory cell transistor is disposed to each intersecting portion of the silicon pillars and laminated word lines. Further, at the upper ends of them, selection transistors are disposed to the respective intersecting portions of the respective ones of the pair of silicon pillars and two selection gates. One of the two selection transistors is connected to a bit line, and the other of the two selection transistors is connected to a source line.
The p-BiCS has a problem in that an increase of the number of laminated layers increases a chip area. This is because the increase of the number of laminated layers increases the number of word line drivers and the number of wirings for connecting word lines to the drivers. It is necessary to suppress an enlargement of a chip area due to the increase of number of the drivers and the wirings.